In the fabrication of integrated circuits an elaborate system of metallized interconnects are utilized to couple together each of the various devices. To achieve these interconnections it is common to employ multiple layers of metal.
Conventionally, the process of forming multiple layers of metal begins by forming an insulative layer over the substrate. This layer (usually silicon dioxide) insulates the substrate from the first metalization layer (metal 1). Openings are etched in the insulative layer to contact the devices. Next, a metal layer--typically aluminum or an aluminum alloy--is deposited over the entire surface of the substrate. This metal 1 layer is then etched to pattern the interconnects. Afterwards, an interlayer dielectric is deposited to insulate metal 1 from the next metallization layer (i.e., metal 2). In many integrated circuits the interlayer dielectric comprises a chemical vapor deposition (CVD) of silicon dioxide. The silicon dioxide layer covers the metal 1 layer such that the upper surface of the silicon dioxide layer is characterized by a series of non-planer steps.
These step variations in the upper surface of the interlayer dielectric have several undesirable features. First, a non-planer dielectric surface interferes with the optical resolution of subsequent photolithographic processing steps. This makes it extremely difficult to print high resolution lines. A second problem involves the step coverage of the metal 2 layer over the interlayer dielectric. If the step height is too large there is a serious danger that open circuits will be formed in the metal 2 layer. Therefore, to decrease these undesirable effects, it is necessary to planarize or polish the upper surface of the deposited dielectric.
The common method employed in polishing an oxidized layer is to place the silicon substrate facedown on a table coated with an abrasive solution. Both the wafer and the table are then rotated relative to each other in an abrasive fashion to remove the protruding steps. After polishing, the substrate is usually dipped in de-ionized water in an attempt to rinse off the abrasive solution. The problem, however, is that this dip is only partially effective in removing the silica particles. A large percentage of silica particles remain imbedded in, or adhere to, the surface of the wafer.
The cause of this phenomena is not entirely understood. It is believed that the particles adhere to the substrate for two reasons. First, the particles may be physically ground into the dielectric layer as a consequence of the abrasive polishing process. Thus, the silica particles may become imbedded in grooves, cracks or other incongruities in the surface of the oxide layer.
It is believed that the second cause for the attraction may be electrostatic in nature. That is, the negative zeta potential (to be described in more detail shortly) surrounding the silica particles attracts them to positive ions present in either the oxide or bulk of the silicon substrate. In any event, removal of these particles following polishing has proven problematic. Obviously, if the residual silica particles remain on the dielectric surface they may produce cracks, opens, shorts or other imperfections in the subsequently deposited metal 2 layer. More generally, it can be stated that the silica particles contaminate each of the subsequent processing steps leading to reduced functionality and lower yield in the finished integrated circuit (IC). What is needed then, is an improved cleaning process which is effective in completely removing all of the abrasive particles from the surface of a polished silicon substrate.